Web Seminar: Making The Right Architectural Decisions
On May 6, from 11 a.m. to noon, Mentor Graphics will examine: How to create a system-level transaction model; Simulation of the TLM to approximate system processing and traffic; How o debug the...
View ArticleExperts At The Table: System-Level Verification
System-Level Design sat down to discuss issues in system-level verification with Frank Schirrmeister, director of product development in Synopsys’ solutions group; Donald Cramb, director of...
View ArticleEnd-User Report: Interoperability Still Lacking With System-Level Power Modeling
All of the major EDA vendors and standards groups are pitching modeling as the next level of abstraction for advanced process nodes, but is it working as planned for the chipmakers? System-Level Design...
View ArticleBlog Review: Feb. 3
By Ed Sperling Synopsys’ Karen Bartleson points to an important—and prematurely short—video from Colin Warwick, a signal integrity expert at Agilent. It’s required watching for anyone working in the...
View ArticleStandards Update
By Ann Steffora Mutschler In the sometimes-murky waters of system-level modeling standards where real-world adoption can be difficult to track, work is progressing to help hardware and software...
View ArticleEDA Experiments With Portals
By Ed Sperling Design complexity is driving vendors much closer to their customers, as companies seek to trade information back and forth with the users of their technology. The latest incarnation of...
View ArticleComprehensive UVM/OVM Acceleration
Today’s traditional design flow involves design at multiple levels of abstraction. As the design implementation is refined and the verification vehicle changes, the testbench needs to adjust to...
View ArticleWhat’s Ahead For System-Level Design
By Ann Steffora Mutschler Architecting an SoC today is incredibly difficult. When you add in the number of available transistors, the manufacturing effects of smaller nodes, IP and software that must...
View ArticleTLM-Driven Design And Verification—Time For A Methodology Shift
While today’s RTL design and verification flows are a step up from the gate-level flows of two decades ago, RTL flows are straining to meet the demands of most product teams. When designs are sourced...
View ArticleBlog Review: Jan. 23
By Ed Sperling Mentor’s Robin Bornoff rolls out part one of his forthcoming epic on experimentation vs. simulation, and how to make sure a product doesn’t fail, doesn’t need tweaking—or get canned...
View ArticleAccellera Systems Initiative has taken over OCP-IP
By Gabe Moretti Accellera has been taking over multiple standards organization in the industry for several years and this is only the latest. The acquisition includes the current OCP 3.0 standard and...
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ASIC Prototyping With FPGA
Zibi Zalewski, General Manger of the Hardware Products Division, Aldec When I began my career as a verification products manager, ASIC/SoC verification was less integrated and the separation among...
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A Prototyping with FPGA Approach
Frank Schirrmeister, Group Director for Product Marketing of the System Development Suite, Cadence. In general, the industry is experiencing the need for what now has been started being called the...
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Rapid Prototyping is an Enduring Methodology
Gabe Moretti, Senior Editor When I started working in the electronic industry hardware development had prototyping using printed circuit boards (PCB) as its only verification tool. The method was not...
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